/***************************************************************************//**
* \file cyip_mxs40usbhsdev.h
*
* \brief
* MXS40USBHSDEV IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_MXS40USBHSDEV_H_
#define _CYIP_MXS40USBHSDEV_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                MXS40USBHSDEV
*******************************************************************************/

#define USBHSDEV_SECTION_SIZE     0x00009400UL
#define USBHSPHY_SECTION_SIZE     0x00000100UL
#define MXS40USBHSDEV_SECTION_SIZE              0x0000A000UL

/**
  * \brief USB 2.0 Device Controller Registers (MXS40USBHSDEV_USBHSDEV)
  */
typedef struct {
  __IOM uint32_t MMIO_EPM_EGRS_SRAM[4096];      /*!< 0x00000000 EPM MMIO Egress SRAM */
  __IOM uint32_t MMIO_EPM_IGRS_SRAM[4096];      /*!< 0x00004000 EPM MMIO Ingress SRAM */
   __IM uint32_t RESERVED[1024];
  __IOM uint32_t DEV_CS;                        /*!< 0x00009000 Device controller Master Control and Status */
   __IM uint32_t DEV_FRAMECNT;                  /*!< 0x00009004 FRAMECNT register */
  __IOM uint32_t DEV_PWR_CS;                    /*!< 0x00009008 Power management control and status */
   __IM uint32_t DEV_SETUPDAT_0;                /*!< 0x0000900C SETUPDAT0 register */
   __IM uint32_t DEV_SETUPDAT_1;                /*!< 0x00009010 SETUPDAT1 register */
  __IOM uint32_t DEV_TOGGLE;                    /*!< 0x00009014 Data toggle for endpoints */
  __IOM uint32_t DEV_EPI_CS[16];                /*!< 0x00009018 IN Endpoint Control and Status register */
  __IOM uint32_t DEV_EPI_XFER_CNT[16];          /*!< 0x00009058 IN Endpoint remaining transfer length register */
  __IOM uint32_t DEV_EPO_CS[16];                /*!< 0x00009098 OUT Endpoint Control and Status */
  __IOM uint32_t DEV_EPO_XFER_CNT[16];          /*!< 0x000090D8 OUT Endpoint remaining transfer length register */
  __IOM uint32_t DEV_CTL_INTR_MASK;             /*!< 0x00009118 CONTROL interrupt mask register */
  __IOM uint32_t DEV_CTL_INTR;                  /*!< 0x0000911C CONTROL interrupt request register */
   __IM uint32_t DEV_CTL_INTR_MASKED;           /*!< 0x00009120 CONTROL interrupt masked register */
  __IOM uint32_t DEV_CTL_INTR_SET;              /*!< 0x00009124 CONTROL interrupt set register */
  __IOM uint32_t DEV_EP_INTR_MASK;              /*!< 0x00009128 USB EP interrupt mask register */
  __IOM uint32_t DEV_EP_INTR;                   /*!< 0x0000912C USB EP interrupt request register */
   __IM uint32_t DEV_EP_INTR_MASKED;            /*!< 0x00009130 USB EP interrupt masked register */
  __IOM uint32_t DEV_EP_INTR_SET;               /*!< 0x00009134 USB EP interrupt set register */
  __IOM uint32_t DEV_EP_INGRS_INTR_MASK;        /*!< 0x00009138 USB EP INGRS interrupt mask register */
  __IOM uint32_t DEV_EP_INGRS_INTR;             /*!< 0x0000913C USB EP INGRS interrupt request register */
   __IM uint32_t DEV_EP_INGRS_INTR_MASKED;      /*!< 0x00009140 USB EP INGRS interrupt masked register */
  __IOM uint32_t DEV_EP_INGRS_INTR_SET;         /*!< 0x00009144 USB EP INGRS interrupt set register */
  __IOM uint32_t DEV_EP_EGRS_REQ;               /*!< 0x00009148 USB EP Egress Request register */
  __IOM uint32_t DEV_EP_EGRS_INTR_MASK;         /*!< 0x0000914C USB EP EGRS interrupt mask register */
  __IOM uint32_t DEV_EP_EGRS_INTR;              /*!< 0x00009150 USB EP EGRS interrupt request register */
   __IM uint32_t DEV_EP_EGRS_INTR_MASKED;       /*!< 0x00009154 USB EP EGRS interrupt masked register */
  __IOM uint32_t DEV_EP_EGRS_INTR_SET;          /*!< 0x00009158 USB EP EGRS interrupt set register */
  __IOM uint32_t POWER;                         /*!< 0x0000915C USB 2.0 Device Power, Clock & Reset Control Register */
  __IOM uint32_t DEV_LPM_ATTR;                  /*!< 0x00009160 USB 2.0 Device LPM Register */
  __IOM uint32_t DEV_LPM_TIM_1;                 /*!< 0x00009164 USB 2.0 Device LPM Timer Parameter Register */
  __IOM uint32_t DEV_CHIRP_OVERRIDE;            /*!< 0x00009168 USB 2.0 Device Chirp Override Register */
  __IOM uint32_t DEV_TIM_T_DCHSE0;              /*!< 0x0000916C USB 2.0 Device Init Timing 0 Register */
  __IOM uint32_t DEV_TIM_T_DETRST_FILT;         /*!< 0x00009170 USB 2.0 Device Init Timing 1 Register */
  __IOM uint32_t DEV_TIM_T_WTFS;                /*!< 0x00009174 USB 2.0 Device Init Timing 2 Register */
  __IOM uint32_t DEV_TIM_T_SUSP;                /*!< 0x00009178 USB 2.0 Device Init Timing 3 Register */
  __IOM uint32_t DEV_TIM_T_WTRSTHS;             /*!< 0x0000917C USB 2.0 Device Init Timing 4 Register */
  __IOM uint32_t DEV_TIM_T_UCH;                 /*!< 0x00009180 USB 2.0 Device Init Timing 5 Register */
  __IOM uint32_t DEV_TIM_T_WTREV_WTRSTFS;       /*!< 0x00009184 USB 2.0 Device Init Timing 6 Register */
  __IOM uint32_t DDFT_CONFIG;                   /*!< 0x00009188 USB 2.0 DDFT Configuration Register */
   __IM uint32_t RESERVED1;
  __IOM uint32_t DEV_LOOPBACK_CTRL;             /*!< 0x00009190 USB 2.0 UTMI Loopback Control Register */
  __IOM uint32_t DEV_LOOPBACK_IN_REQ;           /*!< 0x00009194 USB 2.0 UTMI Loopback IN Token Request Register */
  __IOM uint32_t DEV_LOOPBACK_OUT_REQ;          /*!< 0x00009198 USB 2.0 UTMI Loopback OUT Token Request Register */
   __IM uint32_t RESERVED2[25];
  __IOM uint32_t EPM_CS;                        /*!< 0x00009200 EPM Control and Status Register */
   __IM uint32_t RESERVED3;
   __IM uint32_t EEPM_DEBUG;                    /*!< 0x00009208 Egress EPM Debug Register */
   __IM uint32_t IEPM_DEBUG;                    /*!< 0x0000920C Ingress EPM Debug Register */
   __IM uint32_t IEPM_DEBUG_1;                  /*!< 0x00009210 Ingress EPM Debug 1 Register */
   __IM uint32_t IEPM_DEBUG_2;                  /*!< 0x00009214 Ingress EPM Debug 2 Register */
   __IM uint32_t RESERVED4[2];
  __IOM uint32_t EEPM_ENDPOINT[16];             /*!< 0x00009220 Egress EPM per Endpoint Control and Status */
  __IOM uint32_t IEPM_ENDPOINT[16];             /*!< 0x00009260 Ingress EPM Per Endpoint Control and Status */
   __IM uint32_t EEPM_DEBUG_ENDPOINT[16];       /*!< 0x000092A0 Egress EPM Per Endpoint Debug */
   __IM uint32_t IEPM_DEBUG_ENDPOINT[16];       /*!< 0x000092E0 Ingress EPM Per Endpoint Debug */
  __IOM uint32_t MMIO_EEPM_ENDPOINT[16];        /*!< 0x00009320 MMIO Egress EPM per Endpoint Control and Status */
  __IOM uint32_t MMIO_IEPM_ENDPOINT[16];        /*!< 0x00009360 MMIO Ingress EPM Per Endpoint Control and Status */
  __IOM uint32_t DEV_SPARE_1;                   /*!< 0x000093A0 DEV SPARE 1 Register */
  __IOM uint32_t DEV_SPARE_2;                   /*!< 0x000093A4 DEV SPARE 2 Register */
  __IOM uint32_t LEGACY_FEATURE_ENABLE;         /*!< 0x000093A8 Legacy Feature Enable Register */
   __IM uint32_t DFT_OBSERVE;                   /*!< 0x000093AC DFT Observable Register */
   __IM uint32_t RESERVED5[20];
} USBHSDEV_V1_Type;               /*!< Size = 37888 (0x9400) */

/**
  * \brief USB 2.0 PHY Registers (MXS40USBHSDEV_USBHSPHY)
  */
typedef struct {
  __IOM uint32_t AFE_CONTROL_1;                 /*!< 0x00000000 AFE Control register #1 */
  __IOM uint32_t AFE_CONTROL_2;                 /*!< 0x00000004 AFE Control register #2 */
  __IOM uint32_t UTMI_CONTROL;                  /*!< 0x00000008 UTMI Control register */
  __IOM uint32_t CDR_CONTROL;                   /*!< 0x0000000C CDR registers */
  __IOM uint32_t BC_CONTROL;                    /*!< 0x00000010 UHC Battery Charging CSR Bank */
  __IOM uint32_t PLL_CONTROL_1;                 /*!< 0x00000014 Primary PLL control register#1 */
  __IOM uint32_t PLL_CONTROL_2;                 /*!< 0x00000018 Primary PLL control register#2 */
  __IOM uint32_t TEST_PLL_CONTROL;              /*!< 0x0000001C Test PLL control register */
  __IOM uint32_t TEST_CONTROL;                  /*!< 0x00000020 Test control register */
  __IOM uint32_t DDFT_CFG;                      /*!< 0x00000024 DDFT configuration */
  __IOM uint32_t DIGITAL_CONTROL;               /*!< 0x00000028 Provides control and configuration to digital blocks */
  __IOM uint32_t VREFGEN_CONTROL;               /*!< 0x0000002C VREFGEN control */
  __IOM uint32_t REG_SW_1P2_CONTROL;            /*!< 0x00000030 REG_SW_1P2 control */
  __IOM uint32_t REG_1P1_CONTROL;               /*!< 0x00000034 REG_1P1 control */
  __IOM uint32_t REG_2P5_CONTROL;               /*!< 0x00000038 REG_2P5_ control */
  __IOM uint32_t IREFGEN_CONTROL;               /*!< 0x0000003C IREFGEN_ control */
   __IM uint32_t STATUS;                        /*!< 0x00000040 Status */
  __IOM uint32_t INTR0;                         /*!< 0x00000044 INTR0 Cause. These are the wakeup interrupts get reflected on
                                                                interrupt_wakeup pin. */
  __IOM uint32_t INTR0_SET;                     /*!< 0x00000048 INTR0 Set */
  __IOM uint32_t INTR0_MASK;                    /*!< 0x0000004C INTR0 Mask */
   __IM uint32_t INTR0_MASKED;                  /*!< 0x00000050 INTR0 Masked */
  __IOM uint32_t SPARE;                         /*!< 0x00000054 Spare */
  __IOM uint32_t AFE_CONTROL_3;                 /*!< 0x00000058 AFE Control register #3 */
  __IOM uint32_t AFE_CONTROL_4;                 /*!< 0x0000005C AFE Control register #4 */
  __IOM uint32_t UTMI_CONTROL_2;                /*!< 0x00000060 UTMI Configurtation Registers */
   __IM uint32_t RESERVED[35];
  __IOM uint32_t PLL_TRIMS;                     /*!< 0x000000F0 Trim register for the PLL */
  __IOM uint32_t AFE_TRIMS;                     /*!< 0x000000F4 Trim register for the AFE */
   __IM uint32_t RESERVED1[2];
} USBHSPHY_V1_Type;               /*!< Size = 256 (0x100) */

/**
  * \brief USB 2 Device Controller Memory Register Map (MXS40USBHSDEV)
  */
typedef struct {
        USBHSDEV_V1_Type USBHSDEV; /*!< 0x00000000 USB 2.0 Device Controller Registers */
   __IM uint32_t RESERVED[256];
        USBHSPHY_V1_Type USBHSPHY; /*!< 0x00009800 USB 2.0 PHY Registers */
} MXS40USBHSDEV_V1_Type;                        /*!< Size = 39168 (0x9900) */


/* MXS40USBHSDEV_USBHSDEV.MMIO_EPM_EGRS_SRAM */
#define USBHSDEV_MMIO_EPM_EGRS_SRAM_DATA_Pos 0UL
#define USBHSDEV_MMIO_EPM_EGRS_SRAM_DATA_Msk 0xFFFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.MMIO_EPM_IGRS_SRAM */
#define USBHSDEV_MMIO_EPM_IGRS_SRAM_DATA_Pos 0UL
#define USBHSDEV_MMIO_EPM_IGRS_SRAM_DATA_Msk 0xFFFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_CS */
#define USBHSDEV_DEV_CS_ERR_LIMIT_Pos 0UL
#define USBHSDEV_DEV_CS_ERR_LIMIT_Msk 0xFFUL
#define USBHSDEV_DEV_CS_COUNT_Pos 8UL
#define USBHSDEV_DEV_CS_COUNT_Msk 0xFF00UL
#define USBHSDEV_DEV_CS_DEVICEADDR_Pos 16UL
#define USBHSDEV_DEV_CS_DEVICEADDR_Msk 0x7F0000UL
#define USBHSDEV_DEV_CS_TEST_MODE_Pos 23UL
#define USBHSDEV_DEV_CS_TEST_MODE_Msk 0x3800000UL
#define USBHSDEV_DEV_CS_SETUP_CLR_BUSY_Pos 26UL
#define USBHSDEV_DEV_CS_SETUP_CLR_BUSY_Msk 0x4000000UL
#define USBHSDEV_DEV_CS_CONT_TO_DATA_Pos 27UL
#define USBHSDEV_DEV_CS_CONT_TO_DATA_Msk 0x8000000UL
#define USBHSDEV_DEV_CS_NAKALL_Pos 31UL
#define USBHSDEV_DEV_CS_NAKALL_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_FRAMECNT */
#define USBHSDEV_DEV_FRAMECNT_MICROFRAME_Pos 0UL
#define USBHSDEV_DEV_FRAMECNT_MICROFRAME_Msk 0x7UL
#define USBHSDEV_DEV_FRAMECNT_FRAMECNT_Pos 3UL
#define USBHSDEV_DEV_FRAMECNT_FRAMECNT_Msk 0x3FF8UL
/* MXS40USBHSDEV_USBHSDEV.DEV_PWR_CS */
#define USBHSDEV_DEV_PWR_CS_SIGRSUME_Pos 0UL
#define USBHSDEV_DEV_PWR_CS_SIGRSUME_Msk 0x1UL
#define USBHSDEV_DEV_PWR_CS_NOSYNSOF_Pos 2UL
#define USBHSDEV_DEV_PWR_CS_NOSYNSOF_Msk 0x4UL
#define USBHSDEV_DEV_PWR_CS_DISCON_Pos 3UL
#define USBHSDEV_DEV_PWR_CS_DISCON_Msk 0x8UL
#define USBHSDEV_DEV_PWR_CS_DEV_SUSPEND_Pos 4UL
#define USBHSDEV_DEV_PWR_CS_DEV_SUSPEND_Msk 0x10UL
#define USBHSDEV_DEV_PWR_CS_FORCE_FS_Pos 6UL
#define USBHSDEV_DEV_PWR_CS_FORCE_FS_Msk 0x40UL
#define USBHSDEV_DEV_PWR_CS_HSM_Pos 7UL
#define USBHSDEV_DEV_PWR_CS_HSM_Msk 0x80UL
#define USBHSDEV_DEV_PWR_CS_L0_ACTIVE_Pos 8UL
#define USBHSDEV_DEV_PWR_CS_L0_ACTIVE_Msk 0x100UL
#define USBHSDEV_DEV_PWR_CS_L2_SUSPEND_Pos 9UL
#define USBHSDEV_DEV_PWR_CS_L2_SUSPEND_Msk 0x200UL
#define USBHSDEV_DEV_PWR_CS_L1_SLEEP_Pos 10UL
#define USBHSDEV_DEV_PWR_CS_L1_SLEEP_Msk 0x400UL
/* MXS40USBHSDEV_USBHSDEV.DEV_SETUPDAT_0 */
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_TYPE_Pos 0UL
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_TYPE_Msk 0xFFUL
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_Pos 8UL
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_REQUEST_Msk 0xFF00UL
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_VALUE_Pos 16UL
#define USBHSDEV_DEV_SETUPDAT_0_SETUP_VALUE_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_SETUPDAT_1 */
#define USBHSDEV_DEV_SETUPDAT_1_SETUP_INDEX_Pos 0UL
#define USBHSDEV_DEV_SETUPDAT_1_SETUP_INDEX_Msk 0xFFFFUL
#define USBHSDEV_DEV_SETUPDAT_1_SETUP_LENGTH_Pos 16UL
#define USBHSDEV_DEV_SETUPDAT_1_SETUP_LENGTH_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_TOGGLE */
#define USBHSDEV_DEV_TOGGLE_ENDPOINT_Pos 0UL
#define USBHSDEV_DEV_TOGGLE_ENDPOINT_Msk 0xFUL
#define USBHSDEV_DEV_TOGGLE_IO_Pos 4UL
#define USBHSDEV_DEV_TOGGLE_IO_Msk 0x10UL
#define USBHSDEV_DEV_TOGGLE_R_Pos 5UL
#define USBHSDEV_DEV_TOGGLE_R_Msk 0x20UL
#define USBHSDEV_DEV_TOGGLE_S_Pos 6UL
#define USBHSDEV_DEV_TOGGLE_S_Msk 0x40UL
#define USBHSDEV_DEV_TOGGLE_Q_Pos 7UL
#define USBHSDEV_DEV_TOGGLE_Q_Msk 0x80UL
#define USBHSDEV_DEV_TOGGLE_TOGGLE_VALID_Pos 8UL
#define USBHSDEV_DEV_TOGGLE_TOGGLE_VALID_Msk 0x100UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EPI_CS */
#define USBHSDEV_DEV_EPI_CS_PAYLOAD_Pos 0UL
#define USBHSDEV_DEV_EPI_CS_PAYLOAD_Msk 0x3FFUL
#define USBHSDEV_DEV_EPI_CS_TYPE_Pos 10UL
#define USBHSDEV_DEV_EPI_CS_TYPE_Msk 0xC00UL
#define USBHSDEV_DEV_EPI_CS_ISOINPKS_Pos 12UL
#define USBHSDEV_DEV_EPI_CS_ISOINPKS_Msk 0x3000UL
#define USBHSDEV_DEV_EPI_CS_VALID_Pos 14UL
#define USBHSDEV_DEV_EPI_CS_VALID_Msk 0x4000UL
#define USBHSDEV_DEV_EPI_CS_NAK_Pos 15UL
#define USBHSDEV_DEV_EPI_CS_NAK_Msk 0x8000UL
#define USBHSDEV_DEV_EPI_CS_STALL_Pos 16UL
#define USBHSDEV_DEV_EPI_CS_STALL_Msk 0x10000UL
#define USBHSDEV_DEV_EPI_CS_COMMIT_Pos 18UL
#define USBHSDEV_DEV_EPI_CS_COMMIT_Msk 0x40000UL
#define USBHSDEV_DEV_EPI_CS_BNAK_Pos 19UL
#define USBHSDEV_DEV_EPI_CS_BNAK_Msk 0x80000UL
#define USBHSDEV_DEV_EPI_CS_DONE_Pos 20UL
#define USBHSDEV_DEV_EPI_CS_DONE_Msk 0x100000UL
#define USBHSDEV_DEV_EPI_CS_ZERO_Pos 21UL
#define USBHSDEV_DEV_EPI_CS_ZERO_Msk 0x200000UL
#define USBHSDEV_DEV_EPI_CS_SHORT_Pos 22UL
#define USBHSDEV_DEV_EPI_CS_SHORT_Msk 0x400000UL
#define USBHSDEV_DEV_EPI_CS_ISOERR_Pos 23UL
#define USBHSDEV_DEV_EPI_CS_ISOERR_Msk 0x800000UL
#define USBHSDEV_DEV_EPI_CS_COMMIT_MASK_Pos 26UL
#define USBHSDEV_DEV_EPI_CS_COMMIT_MASK_Msk 0x4000000UL
#define USBHSDEV_DEV_EPI_CS_BNAK_MASK_Pos 27UL
#define USBHSDEV_DEV_EPI_CS_BNAK_MASK_Msk 0x8000000UL
#define USBHSDEV_DEV_EPI_CS_DONE_MASK_Pos 28UL
#define USBHSDEV_DEV_EPI_CS_DONE_MASK_Msk 0x10000000UL
#define USBHSDEV_DEV_EPI_CS_ZERO_MASK_Pos 29UL
#define USBHSDEV_DEV_EPI_CS_ZERO_MASK_Msk 0x20000000UL
#define USBHSDEV_DEV_EPI_CS_SHORT_MASK_Pos 30UL
#define USBHSDEV_DEV_EPI_CS_SHORT_MASK_Msk 0x40000000UL
#define USBHSDEV_DEV_EPI_CS_ISOERR_MASK_Pos 31UL
#define USBHSDEV_DEV_EPI_CS_ISOERR_MASK_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EPI_XFER_CNT */
#define USBHSDEV_DEV_EPI_XFER_CNT_BYTES_REMAINING_Pos 0UL
#define USBHSDEV_DEV_EPI_XFER_CNT_BYTES_REMAINING_Msk 0xFFFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_EPO_CS */
#define USBHSDEV_DEV_EPO_CS_PAYLOAD_Pos 0UL
#define USBHSDEV_DEV_EPO_CS_PAYLOAD_Msk 0x3FFUL
#define USBHSDEV_DEV_EPO_CS_TYPE_Pos 10UL
#define USBHSDEV_DEV_EPO_CS_TYPE_Msk 0xC00UL
#define USBHSDEV_DEV_EPO_CS_ISOINPKS_Pos 12UL
#define USBHSDEV_DEV_EPO_CS_ISOINPKS_Msk 0x3000UL
#define USBHSDEV_DEV_EPO_CS_VALID_Pos 14UL
#define USBHSDEV_DEV_EPO_CS_VALID_Msk 0x4000UL
#define USBHSDEV_DEV_EPO_CS_NAK_Pos 15UL
#define USBHSDEV_DEV_EPO_CS_NAK_Msk 0x8000UL
#define USBHSDEV_DEV_EPO_CS_STALL_Pos 16UL
#define USBHSDEV_DEV_EPO_CS_STALL_Msk 0x10000UL
#define USBHSDEV_DEV_EPO_CS_OVF_Pos 17UL
#define USBHSDEV_DEV_EPO_CS_OVF_Msk 0x20000UL
#define USBHSDEV_DEV_EPO_CS_COMMIT_Pos 18UL
#define USBHSDEV_DEV_EPO_CS_COMMIT_Msk 0x40000UL
#define USBHSDEV_DEV_EPO_CS_BNAK_Pos 19UL
#define USBHSDEV_DEV_EPO_CS_BNAK_Msk 0x80000UL
#define USBHSDEV_DEV_EPO_CS_DONE_Pos 20UL
#define USBHSDEV_DEV_EPO_CS_DONE_Msk 0x100000UL
#define USBHSDEV_DEV_EPO_CS_ZERO_Pos 21UL
#define USBHSDEV_DEV_EPO_CS_ZERO_Msk 0x200000UL
#define USBHSDEV_DEV_EPO_CS_SHORT_Pos 22UL
#define USBHSDEV_DEV_EPO_CS_SHORT_Msk 0x400000UL
#define USBHSDEV_DEV_EPO_CS_ISOERR_Pos 23UL
#define USBHSDEV_DEV_EPO_CS_ISOERR_Msk 0x800000UL
#define USBHSDEV_DEV_EPO_CS_OVF_MASK_Pos 25UL
#define USBHSDEV_DEV_EPO_CS_OVF_MASK_Msk 0x2000000UL
#define USBHSDEV_DEV_EPO_CS_COMMIT_MASK_Pos 26UL
#define USBHSDEV_DEV_EPO_CS_COMMIT_MASK_Msk 0x4000000UL
#define USBHSDEV_DEV_EPO_CS_BNAK_MASK_Pos 27UL
#define USBHSDEV_DEV_EPO_CS_BNAK_MASK_Msk 0x8000000UL
#define USBHSDEV_DEV_EPO_CS_DONE_MASK_Pos 28UL
#define USBHSDEV_DEV_EPO_CS_DONE_MASK_Msk 0x10000000UL
#define USBHSDEV_DEV_EPO_CS_ZERO_MASK_Pos 29UL
#define USBHSDEV_DEV_EPO_CS_ZERO_MASK_Msk 0x20000000UL
#define USBHSDEV_DEV_EPO_CS_SHORT_MASK_Pos 30UL
#define USBHSDEV_DEV_EPO_CS_SHORT_MASK_Msk 0x40000000UL
#define USBHSDEV_DEV_EPO_CS_ISOERR_MASK_Pos 31UL
#define USBHSDEV_DEV_EPO_CS_ISOERR_MASK_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EPO_XFER_CNT */
#define USBHSDEV_DEV_EPO_XFER_CNT_BYTES_REMAINING_Pos 0UL
#define USBHSDEV_DEV_EPO_XFER_CNT_BYTES_REMAINING_Msk 0xFFFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_MASK */
#define USBHSDEV_DEV_CTL_INTR_MASK_SETADDR_Pos 0UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SETADDR_Msk 0x1UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SOF_Pos 1UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SOF_Msk 0x2UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUSP_Pos 2UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUSP_Msk 0x4UL
#define USBHSDEV_DEV_CTL_INTR_MASK_URESET_Pos 3UL
#define USBHSDEV_DEV_CTL_INTR_MASK_URESET_Msk 0x8UL
#define USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT_Pos 4UL
#define USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT_Msk 0x10UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUTOK_Pos 5UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUTOK_Msk 0x20UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUDAV_Pos 6UL
#define USBHSDEV_DEV_CTL_INTR_MASK_SUDAV_Msk 0x40UL
#define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos 7UL
#define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Msk 0x80UL
#define USBHSDEV_DEV_CTL_INTR_MASK_URESUME_Pos 8UL
#define USBHSDEV_DEV_CTL_INTR_MASK_URESUME_Msk 0x100UL
#define USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE_Pos 9UL
#define USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE_Msk 0x200UL
#define USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ_Pos 10UL
#define USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ_Msk 0x400UL
#define USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME_Pos 11UL
#define USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME_Msk 0x800UL
#define USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE_Pos 12UL
#define USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE_Msk 0x1000UL
#define USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED_Pos 13UL
#define USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED_Msk 0x2000UL
#define USBHSDEV_DEV_CTL_INTR_MASK_DPSLP_Pos 14UL
#define USBHSDEV_DEV_CTL_INTR_MASK_DPSLP_Msk 0x4000UL
#define USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK_Pos 15UL
#define USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK_Msk 0x8000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR */
#define USBHSDEV_DEV_CTL_INTR_SETADDR_Pos 0UL
#define USBHSDEV_DEV_CTL_INTR_SETADDR_Msk 0x1UL
#define USBHSDEV_DEV_CTL_INTR_SOF_Pos 1UL
#define USBHSDEV_DEV_CTL_INTR_SOF_Msk 0x2UL
#define USBHSDEV_DEV_CTL_INTR_SUSP_Pos 2UL
#define USBHSDEV_DEV_CTL_INTR_SUSP_Msk 0x4UL
#define USBHSDEV_DEV_CTL_INTR_URESET_Pos 3UL
#define USBHSDEV_DEV_CTL_INTR_URESET_Msk 0x8UL
#define USBHSDEV_DEV_CTL_INTR_HSGRANT_Pos 4UL
#define USBHSDEV_DEV_CTL_INTR_HSGRANT_Msk 0x10UL
#define USBHSDEV_DEV_CTL_INTR_SUTOK_Pos 5UL
#define USBHSDEV_DEV_CTL_INTR_SUTOK_Msk 0x20UL
#define USBHSDEV_DEV_CTL_INTR_SUDAV_Pos 6UL
#define USBHSDEV_DEV_CTL_INTR_SUDAV_Msk 0x40UL
#define USBHSDEV_DEV_CTL_INTR_ERRLIMIT_Pos 7UL
#define USBHSDEV_DEV_CTL_INTR_ERRLIMIT_Msk 0x80UL
#define USBHSDEV_DEV_CTL_INTR_URESUME_Pos 8UL
#define USBHSDEV_DEV_CTL_INTR_URESUME_Msk 0x100UL
#define USBHSDEV_DEV_CTL_INTR_STATUS_STAGE_Pos 9UL
#define USBHSDEV_DEV_CTL_INTR_STATUS_STAGE_Msk 0x200UL
#define USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ_Pos 10UL
#define USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ_Msk 0x400UL
#define USBHSDEV_DEV_CTL_INTR_L1_URESUME_Pos 11UL
#define USBHSDEV_DEV_CTL_INTR_L1_URESUME_Msk 0x800UL
#define USBHSDEV_DEV_CTL_INTR_RESETDONE_Pos 12UL
#define USBHSDEV_DEV_CTL_INTR_RESETDONE_Msk 0x1000UL
#define USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED_Pos 13UL
#define USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED_Msk 0x2000UL
#define USBHSDEV_DEV_CTL_INTR_DPSLP_Pos 14UL
#define USBHSDEV_DEV_CTL_INTR_DPSLP_Msk 0x4000UL
#define USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK_Pos 15UL
#define USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK_Msk 0x8000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_MASKED */
#define USBHSDEV_DEV_CTL_INTR_MASKED_SETADDR_MASKED_Pos 0UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SETADDR_MASKED_Msk 0x1UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SOF_MASKED_Pos 1UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SOF_MASKED_Msk 0x2UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUSP_MASKED_Pos 2UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUSP_MASKED_Msk 0x4UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_URESET_MASKED_Pos 3UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_URESET_MASKED_Msk 0x8UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_HSGRANT_MASKED_Pos 4UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_HSGRANT_MASKED_Msk 0x10UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUTOK_MASKED_Pos 5UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUTOK_MASKED_Msk 0x20UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUDAV_MASKED_Pos 6UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_SUDAV_MASKED_Msk 0x40UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_ERRLIMIT_MASKED_Pos 7UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_ERRLIMIT_MASKED_Msk 0x80UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_URESUME_MASKED_Pos 8UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_URESUME_MASKED_Msk 0x100UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_STATUS_STAGE_MASKED_Pos 9UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_STATUS_STAGE_MASKED_Msk 0x200UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_L1_SLEEP_REQ_MASKED_Pos 10UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_L1_SLEEP_REQ_MASKED_Msk 0x400UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_L1_URESUME_MASKED_Pos 11UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_L1_URESUME_MASKED_Msk 0x800UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_RESETDONE_MASKED_Pos 12UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_RESETDONE_MASKED_Msk 0x1000UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_HOST_URSUME_ARRIVED_MASKED_Pos 13UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_HOST_URSUME_ARRIVED_MASKED_Msk 0x2000UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_DPSLP_MASKED_Pos 14UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_DPSLP_MASKED_Msk 0x4000UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_PID_MISMATCH_ON_NAK_MASKED_Pos 15UL
#define USBHSDEV_DEV_CTL_INTR_MASKED_PID_MISMATCH_ON_NAK_MASKED_Msk 0x8000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_CTL_INTR_SET */
#define USBHSDEV_DEV_CTL_INTR_SET_SETADDR_MASKED_Pos 0UL
#define USBHSDEV_DEV_CTL_INTR_SET_SETADDR_MASKED_Msk 0x1UL
#define USBHSDEV_DEV_CTL_INTR_SET_SOF_MASKED_Pos 1UL
#define USBHSDEV_DEV_CTL_INTR_SET_SOF_MASKED_Msk 0x2UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUSP_MASKED_Pos 2UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUSP_MASKED_Msk 0x4UL
#define USBHSDEV_DEV_CTL_INTR_SET_URESET_MASKED_Pos 3UL
#define USBHSDEV_DEV_CTL_INTR_SET_URESET_MASKED_Msk 0x8UL
#define USBHSDEV_DEV_CTL_INTR_SET_HSGRANT_MASKED_Pos 4UL
#define USBHSDEV_DEV_CTL_INTR_SET_HSGRANT_MASKED_Msk 0x10UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUTOK_MASKED_Pos 5UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUTOK_MASKED_Msk 0x20UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUDAV_MASKED_Pos 6UL
#define USBHSDEV_DEV_CTL_INTR_SET_SUDAV_MASKED_Msk 0x40UL
#define USBHSDEV_DEV_CTL_INTR_SET_ERRLIMIT_MASKED_Pos 7UL
#define USBHSDEV_DEV_CTL_INTR_SET_ERRLIMIT_MASKED_Msk 0x80UL
#define USBHSDEV_DEV_CTL_INTR_SET_URESUME_MASKED_Pos 8UL
#define USBHSDEV_DEV_CTL_INTR_SET_URESUME_MASKED_Msk 0x100UL
#define USBHSDEV_DEV_CTL_INTR_SET_STATUS_STAGE_MASKED_Pos 9UL
#define USBHSDEV_DEV_CTL_INTR_SET_STATUS_STAGE_MASKED_Msk 0x200UL
#define USBHSDEV_DEV_CTL_INTR_SET_L1_SLEEP_REQ_MASKED_Pos 10UL
#define USBHSDEV_DEV_CTL_INTR_SET_L1_SLEEP_REQ_MASKED_Msk 0x400UL
#define USBHSDEV_DEV_CTL_INTR_SET_L1_URESUME_MASKED_Pos 11UL
#define USBHSDEV_DEV_CTL_INTR_SET_L1_URESUME_MASKED_Msk 0x800UL
#define USBHSDEV_DEV_CTL_INTR_SET_RESETDONE_MASKED_Pos 12UL
#define USBHSDEV_DEV_CTL_INTR_SET_RESETDONE_MASKED_Msk 0x1000UL
#define USBHSDEV_DEV_CTL_INTR_SET_HOST_URSUME_ARRIVED_MASKED_Pos 13UL
#define USBHSDEV_DEV_CTL_INTR_SET_HOST_URSUME_ARRIVED_MASKED_Msk 0x2000UL
#define USBHSDEV_DEV_CTL_INTR_SET_DPSLP_MASKED_Pos 14UL
#define USBHSDEV_DEV_CTL_INTR_SET_DPSLP_MASKED_Msk 0x4000UL
#define USBHSDEV_DEV_CTL_INTR_SET_PID_MISMATCH_ON_NAK_MASKED_Pos 15UL
#define USBHSDEV_DEV_CTL_INTR_SET_PID_MISMATCH_ON_NAK_MASKED_Msk 0x8000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_MASK */
#define USBHSDEV_DEV_EP_INTR_MASK_EP_IN_Pos 0UL
#define USBHSDEV_DEV_EP_INTR_MASK_EP_IN_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INTR_MASK_EP_OUT_Pos 16UL
#define USBHSDEV_DEV_EP_INTR_MASK_EP_OUT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR */
#define USBHSDEV_DEV_EP_INTR_EP_IN_Pos 0UL
#define USBHSDEV_DEV_EP_INTR_EP_IN_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INTR_EP_OUT_Pos 16UL
#define USBHSDEV_DEV_EP_INTR_EP_OUT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_MASKED */
#define USBHSDEV_DEV_EP_INTR_MASKED_EP_IN_Pos 0UL
#define USBHSDEV_DEV_EP_INTR_MASKED_EP_IN_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INTR_MASKED_EP_OUT_Pos 16UL
#define USBHSDEV_DEV_EP_INTR_MASKED_EP_OUT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INTR_SET */
#define USBHSDEV_DEV_EP_INTR_SET_EP_IN_Pos 0UL
#define USBHSDEV_DEV_EP_INTR_SET_EP_IN_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INTR_SET_EP_OUT_Pos 16UL
#define USBHSDEV_DEV_EP_INTR_SET_EP_OUT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_MASK */
#define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_ZLP_RCVD_Pos 0UL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_SLP_RCVD_Pos 16UL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASK_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR */
#define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_ZLP_RCVD_Pos 0UL
#define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_SLP_RCVD_Pos 16UL
#define USBHSDEV_DEV_EP_INGRS_INTR_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_MASKED */
#define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_ZLP_RCVD_Pos 0UL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_SLP_RCVD_Pos 16UL
#define USBHSDEV_DEV_EP_INGRS_INTR_MASKED_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_INGRS_INTR_SET */
#define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_ZLP_RCVD_Pos 0UL
#define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_ZLP_RCVD_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_SLP_RCVD_Pos 16UL
#define USBHSDEV_DEV_EP_INGRS_INTR_SET_EP_INGRS_SLP_RCVD_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_REQ */
#define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_ZLP_SENT_Pos 0UL
#define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_SLP_SENT_Pos 16UL
#define USBHSDEV_DEV_EP_EGRS_REQ_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_MASK */
#define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_ZLP_SENT_Pos 0UL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_SLP_SENT_Pos 16UL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASK_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR */
#define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_ZLP_SENT_Pos 0UL
#define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_SLP_SENT_Pos 16UL
#define USBHSDEV_DEV_EP_EGRS_INTR_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_MASKED */
#define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_ZLP_SENT_Pos 0UL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_SLP_SENT_Pos 16UL
#define USBHSDEV_DEV_EP_EGRS_INTR_MASKED_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_EP_EGRS_INTR_SET */
#define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_ZLP_SENT_Pos 0UL
#define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_ZLP_SENT_Msk 0xFFFFUL
#define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_SLP_SENT_Pos 16UL
#define USBHSDEV_DEV_EP_EGRS_INTR_SET_EP_EGRS_SLP_SENT_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.POWER */
#define USBHSDEV_POWER_RESETN_Pos 0UL
#define USBHSDEV_POWER_RESETN_Msk 0x1UL
#define USBHSDEV_POWER_EPM_DCG_ENABLE_Pos 1UL
#define USBHSDEV_POWER_EPM_DCG_ENABLE_Msk 0x2UL
#define USBHSDEV_POWER_AHB2AHB_SCALING_EN_Pos 2UL
#define USBHSDEV_POWER_AHB2AHB_SCALING_EN_Msk 0x4UL
#define USBHSDEV_POWER_LPM_ENABLE_Pos 3UL
#define USBHSDEV_POWER_LPM_ENABLE_Msk 0x8UL
#define USBHSDEV_POWER_VBUS_VALID_Pos 4UL
#define USBHSDEV_POWER_VBUS_VALID_Msk 0x10UL
#define USBHSDEV_POWER_REFCLK_SEL_Pos 5UL
#define USBHSDEV_POWER_REFCLK_SEL_Msk 0x20UL
/* MXS40USBHSDEV_USBHSDEV.DEV_LPM_ATTR */
#define USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE_Pos 0UL
#define USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE_Msk 0x1UL
#define USBHSDEV_DEV_LPM_ATTR_HIRD_Pos 1UL
#define USBHSDEV_DEV_LPM_ATTR_HIRD_Msk 0x1EUL
#define USBHSDEV_DEV_LPM_ATTR_NYET_Pos 5UL
#define USBHSDEV_DEV_LPM_ATTR_NYET_Msk 0x20UL
#define USBHSDEV_DEV_LPM_ATTR_T_L1_TOKEN_RETRY_Pos 8UL
#define USBHSDEV_DEV_LPM_ATTR_T_L1_TOKEN_RETRY_Msk 0xFFFF00UL
#define USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN_Pos 31UL
#define USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_LPM_TIM_1 */
#define USBHSDEV_DEV_LPM_TIM_1_T_L1_DEV_DRV_RESUME_Pos 0UL
#define USBHSDEV_DEV_LPM_TIM_1_T_L1_DEV_DRV_RESUME_Msk 0xFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_CHIRP_OVERRIDE */
#define USBHSDEV_DEV_CHIRP_OVERRIDE_OVERRIDE_FSM_Pos 0UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_OVERRIDE_FSM_Msk 0x1UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_K_Pos 1UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_K_Msk 0x2UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_J_Pos 2UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_CHIRP_J_Msk 0x4UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_STATE_Pos 3UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_STATE_Msk 0xF8UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_SEND_TEST_PACKET_Pos 15UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_SEND_TEST_PACKET_Msk 0x8000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_RCV_TEST_PACKET_Pos 16UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_RCV_TEST_PACKET_Msk 0x10000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_TEST_PACKET_SPEED_Pos 17UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_TEST_PACKET_SPEED_Msk 0x20000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_FS_Pos 18UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_FS_Msk 0x40000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_FS_Pos 19UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_FS_Msk 0x80000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_HS_Pos 20UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_HS_Msk 0x100000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_HS_Pos 21UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_HS_Msk 0x200000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_NO45_Pos 22UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_J_NO45_Msk 0x400000UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_NO45_Pos 23UL
#define USBHSDEV_DEV_CHIRP_OVERRIDE_FORCE_K_NO45_Msk 0x800000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_DCHSE0 */
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_DCHSE0_Pos 0UL
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_DCHSE0_Msk 0x3FFFUL
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_IPG_Pos 16UL
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_IPG_Msk 0x1F0000UL
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_HST_DBOUNCE_Pos 22UL
#define USBHSDEV_DEV_TIM_T_DCHSE0_T_HST_DBOUNCE_Msk 0x7FC00000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_DETRST_FILT */
#define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_DETRST_Pos 0UL
#define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_DETRST_Msk 0xFFFFFUL
#define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_FILT_Pos 20UL
#define USBHSDEV_DEV_TIM_T_DETRST_FILT_T_FILT_Msk 0xFFF00000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTFS */
#define USBHSDEV_DEV_TIM_T_WTFS_T_WTFS_Pos 0UL
#define USBHSDEV_DEV_TIM_T_WTFS_T_WTFS_Msk 0x1FFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_SUSP */
#define USBHSDEV_DEV_TIM_T_SUSP_T_SUSP_Pos 0UL
#define USBHSDEV_DEV_TIM_T_SUSP_T_SUSP_Msk 0x1FFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTRSTHS */
#define USBHSDEV_DEV_TIM_T_WTRSTHS_T_WTRSTHS_Pos 0UL
#define USBHSDEV_DEV_TIM_T_WTRSTHS_T_WTRSTHS_Msk 0xFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_UCH */
#define USBHSDEV_DEV_TIM_T_UCH_T_UCH_Pos 0UL
#define USBHSDEV_DEV_TIM_T_UCH_T_UCH_Msk 0x1FFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_TIM_T_WTREV_WTRSTFS */
#define USBHSDEV_DEV_TIM_T_WTREV_WTRSTFS_T_WTREV_WTRSTFS_Pos 0UL
#define USBHSDEV_DEV_TIM_T_WTREV_WTRSTFS_T_WTREV_WTRSTFS_Msk 0x1FFFFUL
/* MXS40USBHSDEV_USBHSDEV.DDFT_CONFIG */
#define USBHSDEV_DDFT_CONFIG_DDFT0_SEL_Pos 0UL
#define USBHSDEV_DDFT_CONFIG_DDFT0_SEL_Msk 0x7FUL
#define USBHSDEV_DDFT_CONFIG_DDFT0_POLARITY_Pos 15UL
#define USBHSDEV_DDFT_CONFIG_DDFT0_POLARITY_Msk 0x8000UL
#define USBHSDEV_DDFT_CONFIG_DDFT1_SEL_Pos 16UL
#define USBHSDEV_DDFT_CONFIG_DDFT1_SEL_Msk 0x7F0000UL
#define USBHSDEV_DDFT_CONFIG_DDFT1_POLARITY_Pos 31UL
#define USBHSDEV_DDFT_CONFIG_DDFT1_POLARITY_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_CTRL */
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_EN_Pos 0UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_EN_Msk 0x1UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_Pos 1UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_Msk 0x2UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_INTR_Pos 2UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_INTR_Msk 0x4UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASK_Pos 3UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASK_Msk 0x8UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASKED_Pos 4UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_MASKED_Msk 0x10UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_SW_SET_Pos 5UL
#define USBHSDEV_DEV_LOOPBACK_CTRL_LPBK_START_SW_SET_Msk 0x20UL
/* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_IN_REQ */
#define USBHSDEV_DEV_LOOPBACK_IN_REQ_IN_TOKEN_Pos 0UL
#define USBHSDEV_DEV_LOOPBACK_IN_REQ_IN_TOKEN_Msk 0xFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.DEV_LOOPBACK_OUT_REQ */
#define USBHSDEV_DEV_LOOPBACK_OUT_REQ_OUT_TOKEN_Pos 0UL
#define USBHSDEV_DEV_LOOPBACK_OUT_REQ_OUT_TOKEN_Msk 0xFFFFFFUL
/* MXS40USBHSDEV_USBHSDEV.EPM_CS */
#define USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL_Pos 0UL
#define USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL_Msk 0x1UL
#define USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL_Pos 1UL
#define USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL_Msk 0x2UL
#define USBHSDEV_EPM_CS_ALLOW_TRIG_ON_SLP_Pos 2UL
#define USBHSDEV_EPM_CS_ALLOW_TRIG_ON_SLP_Msk 0x4UL
/* MXS40USBHSDEV_USBHSDEV.EEPM_DEBUG */
#define USBHSDEV_EEPM_DEBUG_C_EPNUM_Pos 0UL
#define USBHSDEV_EEPM_DEBUG_C_EPNUM_Msk 0xFUL
#define USBHSDEV_EEPM_DEBUG_C_REQUEST_Pos 4UL
#define USBHSDEV_EEPM_DEBUG_C_REQUEST_Msk 0x30UL
#define USBHSDEV_EEPM_DEBUG_USB_RD_ADDR_Pos 6UL
#define USBHSDEV_EEPM_DEBUG_USB_RD_ADDR_Msk 0x7FFC0UL
#define USBHSDEV_EEPM_DEBUG_AHB_WR_ADDR_Pos 19UL
#define USBHSDEV_EEPM_DEBUG_AHB_WR_ADDR_Msk 0xFFF80000UL
/* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG */
#define USBHSDEV_IEPM_DEBUG_ACTIVE_EP_NUM_Pos 0UL
#define USBHSDEV_IEPM_DEBUG_ACTIVE_EP_NUM_Msk 0xFUL
#define USBHSDEV_IEPM_DEBUG_P_REQUESTS_Pos 4UL
#define USBHSDEV_IEPM_DEBUG_P_REQUESTS_Msk 0x3F0UL
#define USBHSDEV_IEPM_DEBUG_P_REQ_EP_NUM_Pos 16UL
#define USBHSDEV_IEPM_DEBUG_P_REQ_EP_NUM_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_1 */
#define USBHSDEV_IEPM_DEBUG_1_IGRS_USB_WADDR_Pos 0UL
#define USBHSDEV_IEPM_DEBUG_1_IGRS_USB_WADDR_Msk 0x1FFUL
#define USBHSDEV_IEPM_DEBUG_1_IGRS_AHB_RADDR_Pos 16UL
#define USBHSDEV_IEPM_DEBUG_1_IGRS_AHB_RADDR_Msk 0x1FF0000UL
/* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_2 */
#define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_WADDR_Pos 0UL
#define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_WADDR_Msk 0x1FFUL
#define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_RADDR_Pos 16UL
#define USBHSDEV_IEPM_DEBUG_2_IGRS_LAST_RADDR_Msk 0x1FF0000UL
/* MXS40USBHSDEV_USBHSDEV.EEPM_ENDPOINT */
#define USBHSDEV_EEPM_ENDPOINT_EGRS_SLP_BYTE_COUNT_Pos 0UL
#define USBHSDEV_EEPM_ENDPOINT_EGRS_SLP_BYTE_COUNT_Msk 0x3FFUL
#define USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP_Pos 11UL
#define USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP_Msk 0x800UL
/* MXS40USBHSDEV_USBHSDEV.IEPM_ENDPOINT */
#define USBHSDEV_IEPM_ENDPOINT_INGRS_SLP_BYTE_COUNT_Pos 0UL
#define USBHSDEV_IEPM_ENDPOINT_INGRS_SLP_BYTE_COUNT_Msk 0x3FFUL
#define USBHSDEV_IEPM_ENDPOINT_ALLOW_NAK_TILL_DMA_RDY_Pos 11UL
#define USBHSDEV_IEPM_ENDPOINT_ALLOW_NAK_TILL_DMA_RDY_Msk 0x800UL
/* MXS40USBHSDEV_USBHSDEV.EEPM_DEBUG_ENDPOINT */
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_P_REQUESTS_Pos 0UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_P_REQUESTS_Msk 0x3UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_DMA_TRIGGERED_Pos 2UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EGRS_DMA_TRIGGERED_Msk 0x4UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_ADDR_Pos 3UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_ADDR_Msk 0xFFF8UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_ADDR_Pos 16UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_ADDR_Msk 0x1FFF0000UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_SLP_Pos 29UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_NEXT_SLP_Msk 0x20000000UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_SLP_Pos 30UL
#define USBHSDEV_EEPM_DEBUG_ENDPOINT_EP_CURR_SLP_Msk 0x40000000UL
/* MXS40USBHSDEV_USBHSDEV.IEPM_DEBUG_ENDPOINT */
#define USBHSDEV_IEPM_DEBUG_ENDPOINT_INGRS_DMA_TRIGGERED_Pos 0UL
#define USBHSDEV_IEPM_DEBUG_ENDPOINT_INGRS_DMA_TRIGGERED_Msk 0x1UL
/* MXS40USBHSDEV_USBHSDEV.MMIO_EEPM_ENDPOINT */
#define USBHSDEV_MMIO_EEPM_ENDPOINT_EGRS_IF_SELECT_Pos 0UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_EGRS_IF_SELECT_Msk 0x1UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_SEND_Pos 1UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_SEND_Msk 0x2UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_Pos 2UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_Msk 0x4UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASK_Pos 3UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASK_Msk 0x8UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASKED_Pos 4UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_MASKED_Msk 0x10UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_SW_SET_Pos 5UL
#define USBHSDEV_MMIO_EEPM_ENDPOINT_MMIO_EGRS_TR_RCV_SW_SET_Msk 0x20UL
/* MXS40USBHSDEV_USBHSDEV.MMIO_IEPM_ENDPOINT */
#define USBHSDEV_MMIO_IEPM_ENDPOINT_INGRS_IF_SELECT_Pos 0UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_INGRS_IF_SELECT_Msk 0x1UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_SEND_Pos 1UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_SEND_Msk 0x2UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_Pos 2UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_Msk 0x4UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASK_Pos 3UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASK_Msk 0x8UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASKED_Pos 4UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_MASKED_Msk 0x10UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_SW_SET_Pos 5UL
#define USBHSDEV_MMIO_IEPM_ENDPOINT_MMIO_IGRS_TR_RCV_SW_SET_Msk 0x20UL
/* MXS40USBHSDEV_USBHSDEV.DEV_SPARE_1 */
#define USBHSDEV_DEV_SPARE_1_SPARE_1_1_Pos 0UL
#define USBHSDEV_DEV_SPARE_1_SPARE_1_1_Msk 0xFFFFUL
#define USBHSDEV_DEV_SPARE_1_SPARE_1_2_Pos 16UL
#define USBHSDEV_DEV_SPARE_1_SPARE_1_2_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.DEV_SPARE_2 */
#define USBHSDEV_DEV_SPARE_2_SPARE_2_1_Pos 0UL
#define USBHSDEV_DEV_SPARE_2_SPARE_2_1_Msk 0xFFFFUL
#define USBHSDEV_DEV_SPARE_2_SPARE_2_2_Pos 16UL
#define USBHSDEV_DEV_SPARE_2_SPARE_2_2_Msk 0xFFFF0000UL
/* MXS40USBHSDEV_USBHSDEV.LEGACY_FEATURE_ENABLE */
#define USBHSDEV_LEGACY_FEATURE_ENABLE_DATA0_TOG_UPON_STALL_Pos 0UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_DATA0_TOG_UPON_STALL_Msk 0x1UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_CONT_LP_UPON_NO_HOST_RSUME_Pos 1UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_CONT_LP_UPON_NO_HOST_RSUME_Msk 0x2UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_NO_PID_UPDATE_ON_NAK_Pos 2UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_NO_PID_UPDATE_ON_NAK_Msk 0x4UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_RESERVED_Pos 3UL
#define USBHSDEV_LEGACY_FEATURE_ENABLE_RESERVED_Msk 0xFFFFFFF8UL
/* MXS40USBHSDEV_USBHSDEV.DFT_OBSERVE */
#define USBHSDEV_DFT_OBSERVE_DFT_OBSERVE_Pos 0UL
#define USBHSDEV_DFT_OBSERVE_DFT_OBSERVE_Msk 0xFFFFFFFFUL


/* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_1 */
#define USBHSPHY_AFE_CONTROL_1_HS_PRED_DP_SEL_Pos 0UL
#define USBHSPHY_AFE_CONTROL_1_HS_PRED_DP_SEL_Msk 0x3UL
#define USBHSPHY_AFE_CONTROL_1_HS_PRED_DN_SEL_Pos 2UL
#define USBHSPHY_AFE_CONTROL_1_HS_PRED_DN_SEL_Msk 0xCUL
#define USBHSPHY_AFE_CONTROL_1_HS_AMP_SEL_Pos 4UL
#define USBHSPHY_AFE_CONTROL_1_HS_AMP_SEL_Msk 0xF0UL
#define USBHSPHY_AFE_CONTROL_1_HS_PREE_SEL_Pos 8UL
#define USBHSPHY_AFE_CONTROL_1_HS_PREE_SEL_Msk 0x700UL
#define USBHSPHY_AFE_CONTROL_1_HS_SR_FINE_SEL_Pos 11UL
#define USBHSPHY_AFE_CONTROL_1_HS_SR_FINE_SEL_Msk 0x3800UL
#define USBHSPHY_AFE_CONTROL_1_HS_TED_LP_MODE_Pos 14UL
#define USBHSPHY_AFE_CONTROL_1_HS_TED_LP_MODE_Msk 0x4000UL
#define USBHSPHY_AFE_CONTROL_1_EN_LANE_SWAP_Pos 15UL
#define USBHSPHY_AFE_CONTROL_1_EN_LANE_SWAP_Msk 0x8000UL
#define USBHSPHY_AFE_CONTROL_1_HS_CTLE_SEL_Pos 16UL
#define USBHSPHY_AFE_CONTROL_1_HS_CTLE_SEL_Msk 0x70000UL
#define USBHSPHY_AFE_CONTROL_1_FS_VTRIG_SEL_Pos 19UL
#define USBHSPHY_AFE_CONTROL_1_FS_VTRIG_SEL_Msk 0x380000UL
#define USBHSPHY_AFE_CONTROL_1_FS_SR_SEL_Pos 22UL
#define USBHSPHY_AFE_CONTROL_1_FS_SR_SEL_Msk 0x3C00000UL
#define USBHSPHY_AFE_CONTROL_1_LS_SR_SEL_Pos 26UL
#define USBHSPHY_AFE_CONTROL_1_LS_SR_SEL_Msk 0xC000000UL
#define USBHSPHY_AFE_CONTROL_1_HS_LB_EN_Pos 28UL
#define USBHSPHY_AFE_CONTROL_1_HS_LB_EN_Msk 0x10000000UL
#define USBHSPHY_AFE_CONTROL_1_HS_TED_25_MODE_Pos 29UL
#define USBHSPHY_AFE_CONTROL_1_HS_TED_25_MODE_Msk 0x20000000UL
#define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD_Pos 30UL
#define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD_Msk 0x40000000UL
#define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD_Pos 31UL
#define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_2 */
#define USBHSPHY_AFE_CONTROL_2_AFE_DFT_SEL_Pos 0UL
#define USBHSPHY_AFE_CONTROL_2_AFE_DFT_SEL_Msk 0x3FFUL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_CRUDE_EN_Pos 10UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_CRUDE_EN_Msk 0x400UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MUX_SEL_Pos 11UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MUX_SEL_Msk 0x800UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_OVERRIDE_Pos 12UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_OVERRIDE_Msk 0x1000UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MISSION_EN_Pos 13UL
#define USBHSPHY_AFE_CONTROL_2_EUSB_RX_MISSION_EN_Msk 0x2000UL
#define USBHSPHY_AFE_CONTROL_2_SE_RX_SE1_FILTER_EN_N_Pos 14UL
#define USBHSPHY_AFE_CONTROL_2_SE_RX_SE1_FILTER_EN_N_Msk 0x4000UL
#define USBHSPHY_AFE_CONTROL_2_ENABLE_EUSB_RX_Pos 17UL
#define USBHSPHY_AFE_CONTROL_2_ENABLE_EUSB_RX_Msk 0x20000UL
/* MXS40USBHSDEV_USBHSPHY.UTMI_CONTROL */
#define USBHSPHY_UTMI_CONTROL_SOFT_DISCONNECT_N_Pos 0UL
#define USBHSPHY_UTMI_CONTROL_SOFT_DISCONNECT_N_Msk 0x1UL
#define USBHSPHY_UTMI_CONTROL_VLOAD_Pos 1UL
#define USBHSPHY_UTMI_CONTROL_VLOAD_Msk 0x2UL
#define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTCODE_Pos 2UL
#define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTCODE_Msk 0x3CUL
#define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTDATA_Pos 6UL
#define USBHSPHY_UTMI_CONTROL_VCONTROL_TESTDATA_Msk 0x3C0UL
#define USBHSPHY_UTMI_CONTROL_BIST_EN_Pos 10UL
#define USBHSPHY_UTMI_CONTROL_BIST_EN_Msk 0x400UL
#define USBHSPHY_UTMI_CONTROL_TUNE_BYPASS_EN_Pos 11UL
#define USBHSPHY_UTMI_CONTROL_TUNE_BYPASS_EN_Msk 0x800UL
#define USBHSPHY_UTMI_CONTROL_EXT_CAL_VALUE_Pos 12UL
#define USBHSPHY_UTMI_CONTROL_EXT_CAL_VALUE_Msk 0x1F000UL
#define USBHSPHY_UTMI_CONTROL_OTG_IN_SUSPEND_Pos 17UL
#define USBHSPHY_UTMI_CONTROL_OTG_IN_SUSPEND_Msk 0x20000UL
#define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_EN_Pos 18UL
#define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_EN_Msk 0x40000UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_COMBO_SEQ_Pos 19UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_COMBO_SEQ_Msk 0x80000UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_EXT_SEL_Pos 20UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_EXT_SEL_Msk 0x100000UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_CLK_SEL_Pos 21UL
#define USBHSPHY_UTMI_CONTROL_LINESTATE_CLK_SEL_Msk 0x200000UL
#define USBHSPHY_UTMI_CONTROL_CAL_BIG_LITTLE_ENDIAN_Pos 22UL
#define USBHSPHY_UTMI_CONTROL_CAL_BIG_LITTLE_ENDIAN_Msk 0x400000UL
#define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_PATTERN_Pos 23UL
#define USBHSPHY_UTMI_CONTROL_BIST_CONTINOUS_PATTERN_Msk 0x7F800000UL
#define USBHSPHY_UTMI_CONTROL_REVERT_RPU_CTRL_Pos 31UL
#define USBHSPHY_UTMI_CONTROL_REVERT_RPU_CTRL_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.CDR_CONTROL */
#define USBHSPHY_CDR_CONTROL_CONF_EOI_VEC_Pos 0UL
#define USBHSPHY_CDR_CONTROL_CONF_EOI_VEC_Msk 0x7UL
#define USBHSPHY_CDR_CONTROL_CONF_HS_6_SYNC_Pos 3UL
#define USBHSPHY_CDR_CONTROL_CONF_HS_6_SYNC_Msk 0x8UL
#define USBHSPHY_CDR_CONTROL_EBUF_DEPTH_Pos 4UL
#define USBHSPHY_CDR_CONTROL_EBUF_DEPTH_Msk 0x30UL
#define USBHSPHY_CDR_CONTROL_CDR_CONFIG_1_Pos 6UL
#define USBHSPHY_CDR_CONTROL_CDR_CONFIG_1_Msk 0x40UL
#define USBHSPHY_CDR_CONTROL_CDR_ENABLE_Pos 7UL
#define USBHSPHY_CDR_CONTROL_CDR_ENABLE_Msk 0x80UL
#define USBHSPHY_CDR_CONTROL_SQUELCH_FILTER_Pos 8UL
#define USBHSPHY_CDR_CONTROL_SQUELCH_FILTER_Msk 0x700UL
#define USBHSPHY_CDR_CONTROL_SYNC_MATCH_PATTERN_Pos 11UL
#define USBHSPHY_CDR_CONTROL_SYNC_MATCH_PATTERN_Msk 0x800UL
#define USBHSPHY_CDR_CONTROL_GATE_SERIAL_IN_TILL_SQUELCH_Pos 12UL
#define USBHSPHY_CDR_CONTROL_GATE_SERIAL_IN_TILL_SQUELCH_Msk 0x1000UL
#define USBHSPHY_CDR_CONTROL_SERIAL_IN_DELAY_Pos 13UL
#define USBHSPHY_CDR_CONTROL_SERIAL_IN_DELAY_Msk 0xE000UL
/* MXS40USBHSDEV_USBHSPHY.BC_CONTROL */
#define USBHSPHY_BC_CONTROL_CHRGR_DET_ON_Pos 0UL
#define USBHSPHY_BC_CONTROL_CHRGR_DET_ON_Msk 0x1UL
#define USBHSPHY_BC_CONTROL_VDM_SRC_EN_Pos 1UL
#define USBHSPHY_BC_CONTROL_VDM_SRC_EN_Msk 0x2UL
#define USBHSPHY_BC_CONTROL_VDP_SRC_EN_Pos 2UL
#define USBHSPHY_BC_CONTROL_VDP_SRC_EN_Msk 0x4UL
/* MXS40USBHSDEV_USBHSPHY.PLL_CONTROL_1 */
#define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DEL_Pos 0UL
#define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DEL_Msk 0x3UL
#define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DIS_Pos 2UL
#define USBHSPHY_PLL_CONTROL_1_RUN_AWAY_DIS_Msk 0x4UL
#define USBHSPHY_PLL_CONTROL_1_VCO_GAIN_Pos 3UL
#define USBHSPHY_PLL_CONTROL_1_VCO_GAIN_Msk 0x78UL
#define USBHSPHY_PLL_CONTROL_1_PLL_EN_Pos 8UL
#define USBHSPHY_PLL_CONTROL_1_PLL_EN_Msk 0x100UL
#define USBHSPHY_PLL_CONTROL_1_SUPPLY_EN_Pos 9UL
#define USBHSPHY_PLL_CONTROL_1_SUPPLY_EN_Msk 0x200UL
#define USBHSPHY_PLL_CONTROL_1_LD_DELAY_Pos 10UL
#define USBHSPHY_PLL_CONTROL_1_LD_DELAY_Msk 0xC00UL
#define USBHSPHY_PLL_CONTROL_1_LDO_VCO_BYPASS_Pos 13UL
#define USBHSPHY_PLL_CONTROL_1_LDO_VCO_BYPASS_Msk 0x2000UL
#define USBHSPHY_PLL_CONTROL_1_P_DIV_Pos 14UL
#define USBHSPHY_PLL_CONTROL_1_P_DIV_Msk 0xC000UL
#define USBHSPHY_PLL_CONTROL_1_Q_DIV_Pos 16UL
#define USBHSPHY_PLL_CONTROL_1_Q_DIV_Msk 0x30000UL
#define USBHSPHY_PLL_CONTROL_1_PLL_SPARE_Pos 18UL
#define USBHSPHY_PLL_CONTROL_1_PLL_SPARE_Msk 0x40000UL
#define USBHSPHY_PLL_CONTROL_1_VCO_INIT_DIS_Pos 19UL
#define USBHSPHY_PLL_CONTROL_1_VCO_INIT_DIS_Msk 0x80000UL
#define USBHSPHY_PLL_CONTROL_1_ATST_SEL_Pos 20UL
#define USBHSPHY_PLL_CONTROL_1_ATST_SEL_Msk 0xF00000UL
#define USBHSPHY_PLL_CONTROL_1_CAL_UP_DN_Pos 24UL
#define USBHSPHY_PLL_CONTROL_1_CAL_UP_DN_Msk 0xF000000UL
#define USBHSPHY_PLL_CONTROL_1_RA_UP_TR_Pos 28UL
#define USBHSPHY_PLL_CONTROL_1_RA_UP_TR_Msk 0x30000000UL
/* MXS40USBHSDEV_USBHSPHY.PLL_CONTROL_2 */
#define USBHSPHY_PLL_CONTROL_2_EN_CPU_OVERIDE_PLL_LOCK_Pos 0UL
#define USBHSPHY_PLL_CONTROL_2_EN_CPU_OVERIDE_PLL_LOCK_Msk 0x1UL
#define USBHSPHY_PLL_CONTROL_2_CPU_OVERIDE_PLL_LOCK_VALUE_Pos 1UL
#define USBHSPHY_PLL_CONTROL_2_CPU_OVERIDE_PLL_LOCK_VALUE_Msk 0x2UL
#define USBHSPHY_PLL_CONTROL_2_SOURCE_OF_PLL_LOCK_Pos 2UL
#define USBHSPHY_PLL_CONTROL_2_SOURCE_OF_PLL_LOCK_Msk 0x4UL
#define USBHSPHY_PLL_CONTROL_2_LOCK_DELAY_Pos 3UL
#define USBHSPHY_PLL_CONTROL_2_LOCK_DELAY_Msk 0x7F8UL
#define USBHSPHY_PLL_CONTROL_2_LOSS_LOCK_DELAY_Pos 11UL
#define USBHSPHY_PLL_CONTROL_2_LOSS_LOCK_DELAY_Msk 0xF800UL
#define USBHSPHY_PLL_CONTROL_2_JITTER_TEST_MODE_Pos 16UL
#define USBHSPHY_PLL_CONTROL_2_JITTER_TEST_MODE_Msk 0x10000UL
#define USBHSPHY_PLL_CONTROL_2_DIV_VALUE_Pos 25UL
#define USBHSPHY_PLL_CONTROL_2_DIV_VALUE_Msk 0x1E000000UL
#define USBHSPHY_PLL_CONTROL_2_PLL_CLKOUT_DDFT_SEL_Pos 29UL
#define USBHSPHY_PLL_CONTROL_2_PLL_CLKOUT_DDFT_SEL_Msk 0xE0000000UL
/* MXS40USBHSDEV_USBHSPHY.TEST_PLL_CONTROL */
#define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DEL_Pos 0UL
#define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DEL_Msk 0x3UL
#define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DIS_Pos 2UL
#define USBHSPHY_TEST_PLL_CONTROL_RUN_AWAY_DIS_Msk 0x4UL
#define USBHSPHY_TEST_PLL_CONTROL_VCO_GAIN_Pos 3UL
#define USBHSPHY_TEST_PLL_CONTROL_VCO_GAIN_Msk 0x78UL
#define USBHSPHY_TEST_PLL_CONTROL_PLL_EN_Pos 8UL
#define USBHSPHY_TEST_PLL_CONTROL_PLL_EN_Msk 0x100UL
#define USBHSPHY_TEST_PLL_CONTROL_SUPPLY_EN_Pos 9UL
#define USBHSPHY_TEST_PLL_CONTROL_SUPPLY_EN_Msk 0x200UL
#define USBHSPHY_TEST_PLL_CONTROL_LD_DELAY_Pos 10UL
#define USBHSPHY_TEST_PLL_CONTROL_LD_DELAY_Msk 0xC00UL
#define USBHSPHY_TEST_PLL_CONTROL_LDO_VCO_BYPASS_Pos 13UL
#define USBHSPHY_TEST_PLL_CONTROL_LDO_VCO_BYPASS_Msk 0x2000UL
#define USBHSPHY_TEST_PLL_CONTROL_P_DIV_Pos 14UL
#define USBHSPHY_TEST_PLL_CONTROL_P_DIV_Msk 0xC000UL
#define USBHSPHY_TEST_PLL_CONTROL_Q_DIV_Pos 16UL
#define USBHSPHY_TEST_PLL_CONTROL_Q_DIV_Msk 0x30000UL
#define USBHSPHY_TEST_PLL_CONTROL_PLL_SPARE_Pos 18UL
#define USBHSPHY_TEST_PLL_CONTROL_PLL_SPARE_Msk 0x40000UL
#define USBHSPHY_TEST_PLL_CONTROL_VCO_INIT_DIS_Pos 19UL
#define USBHSPHY_TEST_PLL_CONTROL_VCO_INIT_DIS_Msk 0x80000UL
#define USBHSPHY_TEST_PLL_CONTROL_ATST_SEL_Pos 20UL
#define USBHSPHY_TEST_PLL_CONTROL_ATST_SEL_Msk 0xF00000UL
#define USBHSPHY_TEST_PLL_CONTROL_CAL_UP_DN_Pos 24UL
#define USBHSPHY_TEST_PLL_CONTROL_CAL_UP_DN_Msk 0xF000000UL
#define USBHSPHY_TEST_PLL_CONTROL_RA_UP_TR_Pos 28UL
#define USBHSPHY_TEST_PLL_CONTROL_RA_UP_TR_Msk 0x30000000UL
#define USBHSPHY_TEST_PLL_CONTROL_TEST_LOCK_DELAY_Pos 30UL
#define USBHSPHY_TEST_PLL_CONTROL_TEST_LOCK_DELAY_Msk 0xC0000000UL
/* MXS40USBHSDEV_USBHSPHY.TEST_CONTROL */
#define USBHSPHY_TEST_CONTROL_RUN_CALIBRATION_Pos 0UL
#define USBHSPHY_TEST_CONTROL_RUN_CALIBRATION_Msk 0x1UL
#define USBHSPHY_TEST_CONTROL_CALIBRATED_VALUE_Pos 1UL
#define USBHSPHY_TEST_CONTROL_CALIBRATED_VALUE_Msk 0x3EUL
/* MXS40USBHSDEV_USBHSPHY.DDFT_CFG */
#define USBHSPHY_DDFT_CFG_DDFT0_SEL_Pos 0UL
#define USBHSPHY_DDFT_CFG_DDFT0_SEL_Msk 0x7FUL
#define USBHSPHY_DDFT_CFG_DDFT0_POLARITY_Pos 7UL
#define USBHSPHY_DDFT_CFG_DDFT0_POLARITY_Msk 0x80UL
#define USBHSPHY_DDFT_CFG_DDFT1_SEL_Pos 8UL
#define USBHSPHY_DDFT_CFG_DDFT1_SEL_Msk 0x7F00UL
#define USBHSPHY_DDFT_CFG_DDFT1_POLARITY_Pos 15UL
#define USBHSPHY_DDFT_CFG_DDFT1_POLARITY_Msk 0x8000UL
/* MXS40USBHSDEV_USBHSPHY.DIGITAL_CONTROL */
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_SEL_Pos 0UL
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_SEL_Msk 0x3UL
#define USBHSPHY_DIGITAL_CONTROL_TX_CLOCK_SOURCE_DFT_Pos 2UL
#define USBHSPHY_DIGITAL_CONTROL_TX_CLOCK_SOURCE_DFT_Msk 0x4UL
#define USBHSPHY_DIGITAL_CONTROL_CLK480_PHASE_SEL_Pos 3UL
#define USBHSPHY_DIGITAL_CONTROL_CLK480_PHASE_SEL_Msk 0x8UL
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_ON_DELAY_Pos 5UL
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_ON_DELAY_Msk 0xE0UL
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_OFF_DELAY_Pos 8UL
#define USBHSPHY_DIGITAL_CONTROL_DLAUNCH_OFF_DELAY_Msk 0x700UL
#define USBHSPHY_DIGITAL_CONTROL_BURN_IN_EN_Pos 11UL
#define USBHSPHY_DIGITAL_CONTROL_BURN_IN_EN_Msk 0x800UL
#define USBHSPHY_DIGITAL_CONTROL_BURN_Pos 12UL
#define USBHSPHY_DIGITAL_CONTROL_BURN_Msk 0x3000UL
#define USBHSPHY_DIGITAL_CONTROL_DIS_PRE_EMPHASIS_HS_SOF_Pos 14UL
#define USBHSPHY_DIGITAL_CONTROL_DIS_PRE_EMPHASIS_HS_SOF_Msk 0x4000UL
#define USBHSPHY_DIGITAL_CONTROL_BIT_TIME_DIS_PRE_EMPHASIS_Pos 16UL
#define USBHSPHY_DIGITAL_CONTROL_BIT_TIME_DIS_PRE_EMPHASIS_Msk 0x3F0000UL
#define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_IN_Pos 22UL
#define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_IN_Msk 0x400000UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DP_VALUE_Pos 23UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DP_VALUE_Msk 0x800000UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DN_VALUE_Pos 24UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_IN_DN_VALUE_Msk 0x1000000UL
#define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_PREE_Pos 25UL
#define USBHSPHY_DIGITAL_CONTROL_CONTROL_HS_TX_PREE_Msk 0x2000000UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DP_VALUE_Pos 26UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DP_VALUE_Msk 0x4000000UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DN_VALUE_Pos 27UL
#define USBHSPHY_DIGITAL_CONTROL_HX_TX_PREE_DN_VALUE_Msk 0x8000000UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_CDR_CLK480M_Pos 29UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_CDR_CLK480M_Msk 0x20000000UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M_Pos 30UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSRX_CLK480M_Msk 0x40000000UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M_Pos 31UL
#define USBHSPHY_DIGITAL_CONTROL_DISABLE_POWER_SAVING_UTMI_HSTX_CLK480M_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.VREFGEN_CONTROL */
#define USBHSPHY_VREFGEN_CONTROL_TED_SEL_0_Pos 0UL
#define USBHSPHY_VREFGEN_CONTROL_TED_SEL_0_Msk 0xFUL
#define USBHSPHY_VREFGEN_CONTROL_TED_SEL_1_Pos 4UL
#define USBHSPHY_VREFGEN_CONTROL_TED_SEL_1_Msk 0xF0UL
#define USBHSPHY_VREFGEN_CONTROL_DED_SEL_0_Pos 8UL
#define USBHSPHY_VREFGEN_CONTROL_DED_SEL_0_Msk 0xF00UL
#define USBHSPHY_VREFGEN_CONTROL_DED_SEL_1_Pos 12UL
#define USBHSPHY_VREFGEN_CONTROL_DED_SEL_1_Msk 0xF000UL
#define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_CTRL_Pos 16UL
#define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_CTRL_Msk 0xF0000UL
#define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_EN_Pos 20UL
#define USBHSPHY_VREFGEN_CONTROL_VREFGEN_ADFT_EN_Msk 0x100000UL
#define USBHSPHY_VREFGEN_CONTROL_ENABLE_LV_Pos 31UL
#define USBHSPHY_VREFGEN_CONTROL_ENABLE_LV_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.REG_SW_1P2_CONTROL */
#define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_CTRL_Pos 0UL
#define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_CTRL_Msk 0xFUL
#define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_EN_Pos 4UL
#define USBHSPHY_REG_SW_1P2_CONTROL_SW_ADFT_EN_Msk 0x10UL
#define USBHSPHY_REG_SW_1P2_CONTROL_USE_REG_Pos 5UL
#define USBHSPHY_REG_SW_1P2_CONTROL_USE_REG_Msk 0x20UL
#define USBHSPHY_REG_SW_1P2_CONTROL_ENABLE_LV_Pos 31UL
#define USBHSPHY_REG_SW_1P2_CONTROL_ENABLE_LV_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.REG_1P1_CONTROL */
#define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_CTRL_Pos 0UL
#define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_CTRL_Msk 0xFUL
#define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_EN_Pos 4UL
#define USBHSPHY_REG_1P1_CONTROL_ONEP1_ADFT_EN_Msk 0x10UL
#define USBHSPHY_REG_1P1_CONTROL_SWITCH_EN_Pos 8UL
#define USBHSPHY_REG_1P1_CONTROL_SWITCH_EN_Msk 0x100UL
#define USBHSPHY_REG_1P1_CONTROL_ENABLE_LV_Pos 31UL
#define USBHSPHY_REG_1P1_CONTROL_ENABLE_LV_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.REG_2P5_CONTROL */
#define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_CTRL_Pos 0UL
#define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_CTRL_Msk 0xFUL
#define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_EN_Pos 4UL
#define USBHSPHY_REG_2P5_CONTROL_TWOP5_ADFT_EN_Msk 0x10UL
#define USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE_Pos 8UL
#define USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE_Msk 0x100UL
#define USBHSPHY_REG_2P5_CONTROL_ENABLE_LV_Pos 31UL
#define USBHSPHY_REG_2P5_CONTROL_ENABLE_LV_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.IREFGEN_CONTROL */
#define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_CTRL_Pos 0UL
#define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_CTRL_Msk 0xFUL
#define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_EN_Pos 4UL
#define USBHSPHY_IREFGEN_CONTROL_IREF_ADFT_EN_Msk 0x10UL
#define USBHSPHY_IREFGEN_CONTROL_BYPASS_MODE_Pos 8UL
#define USBHSPHY_IREFGEN_CONTROL_BYPASS_MODE_Msk 0x100UL
#define USBHSPHY_IREFGEN_CONTROL_ENABLE_LV_Pos 31UL
#define USBHSPHY_IREFGEN_CONTROL_ENABLE_LV_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.STATUS */
#define USBHSPHY_STATUS_PLL_LOCK_Pos 0UL
#define USBHSPHY_STATUS_PLL_LOCK_Msk 0x1UL
#define USBHSPHY_STATUS_TEST_PLL_LOCK_Pos 2UL
#define USBHSPHY_STATUS_TEST_PLL_LOCK_Msk 0x4UL
#define USBHSPHY_STATUS_VSTATUSTESTER_Pos 3UL
#define USBHSPHY_STATUS_VSTATUSTESTER_Msk 0x7F8UL
#define USBHSPHY_STATUS_LBSTATUS_Pos 11UL
#define USBHSPHY_STATUS_LBSTATUS_Msk 0x7F800UL
#define USBHSPHY_STATUS_LINE_STATE_Pos 19UL
#define USBHSPHY_STATUS_LINE_STATE_Msk 0x180000UL
#define USBHSPHY_STATUS_HOST_DISCONNECT_Pos 21UL
#define USBHSPHY_STATUS_HOST_DISCONNECT_Msk 0x200000UL
#define USBHSPHY_STATUS_PLL_LOSS_CNT_Pos 22UL
#define USBHSPHY_STATUS_PLL_LOSS_CNT_Msk 0x3C00000UL
#define USBHSPHY_STATUS_BISTOK_Pos 26UL
#define USBHSPHY_STATUS_BISTOK_Msk 0x4000000UL
/* MXS40USBHSDEV_USBHSPHY.INTR0 */
#define USBHSPHY_INTR0_PLL_LOCK_Pos 0UL
#define USBHSPHY_INTR0_PLL_LOCK_Msk 0x1UL
#define USBHSPHY_INTR0_PLL_LOSS_Pos 1UL
#define USBHSPHY_INTR0_PLL_LOSS_Msk 0x2UL
#define USBHSPHY_INTR0_TEST_PLL_LOCK_Pos 2UL
#define USBHSPHY_INTR0_TEST_PLL_LOCK_Msk 0x4UL
#define USBHSPHY_INTR0_PLL_RUN_AWAY_STICKY_CHANGE_Pos 3UL
#define USBHSPHY_INTR0_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x8UL
#define USBHSPHY_INTR0_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Pos 4UL
#define USBHSPHY_INTR0_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x10UL
#define USBHSPHY_INTR0_ENABLE_VCCD_Pos 5UL
#define USBHSPHY_INTR0_ENABLE_VCCD_Msk 0x20UL
#define USBHSPHY_INTR0_ENABLE_HS_VCCD_Pos 6UL
#define USBHSPHY_INTR0_ENABLE_HS_VCCD_Msk 0x40UL
#define USBHSPHY_INTR0_BISTDONE_Pos 7UL
#define USBHSPHY_INTR0_BISTDONE_Msk 0x80UL
#define USBHSPHY_INTR0_ERRORFLOW_Pos 8UL
#define USBHSPHY_INTR0_ERRORFLOW_Msk 0x100UL
#define USBHSPHY_INTR0_STRESS_OUT_Pos 9UL
#define USBHSPHY_INTR0_STRESS_OUT_Msk 0x200UL
#define USBHSPHY_INTR0_CAL_DONE_Pos 10UL
#define USBHSPHY_INTR0_CAL_DONE_Msk 0x400UL
/* MXS40USBHSDEV_USBHSPHY.INTR0_SET */
#define USBHSPHY_INTR0_SET_PLL_LOCK_Pos 0UL
#define USBHSPHY_INTR0_SET_PLL_LOCK_Msk 0x1UL
#define USBHSPHY_INTR0_SET_PLL_LOSS_Pos 1UL
#define USBHSPHY_INTR0_SET_PLL_LOSS_Msk 0x2UL
#define USBHSPHY_INTR0_SET_TEST_PLL_LOCK_Pos 2UL
#define USBHSPHY_INTR0_SET_TEST_PLL_LOCK_Msk 0x4UL
#define USBHSPHY_INTR0_SET_PLL_RUN_AWAY_STICKY_CHANGE_Pos 3UL
#define USBHSPHY_INTR0_SET_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x8UL
#define USBHSPHY_INTR0_SET_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Pos 4UL
#define USBHSPHY_INTR0_SET_TEST_PLL_RUN_AWAY_STICKY_CHANGE_Msk 0x10UL
#define USBHSPHY_INTR0_SET_ENABLE_VCCD_Pos 5UL
#define USBHSPHY_INTR0_SET_ENABLE_VCCD_Msk 0x20UL
#define USBHSPHY_INTR0_SET_ENABLE_HS_VCCD_Pos 6UL
#define USBHSPHY_INTR0_SET_ENABLE_HS_VCCD_Msk 0x40UL
#define USBHSPHY_INTR0_SET_BISTDONE_Pos 7UL
#define USBHSPHY_INTR0_SET_BISTDONE_Msk 0x80UL
#define USBHSPHY_INTR0_SET_ERRORFLOW_Pos 8UL
#define USBHSPHY_INTR0_SET_ERRORFLOW_Msk 0x100UL
#define USBHSPHY_INTR0_SET_STRESS_OUT_Pos 9UL
#define USBHSPHY_INTR0_SET_STRESS_OUT_Msk 0x200UL
#define USBHSPHY_INTR0_SET_CAL_DONE_Pos 10UL
#define USBHSPHY_INTR0_SET_CAL_DONE_Msk 0x400UL
/* MXS40USBHSDEV_USBHSPHY.INTR0_MASK */
#define USBHSPHY_INTR0_MASK_PLL_LOCK_MASK_Pos 0UL
#define USBHSPHY_INTR0_MASK_PLL_LOCK_MASK_Msk 0x1UL
#define USBHSPHY_INTR0_MASK_PLL_LOSS_MASK_Pos 1UL
#define USBHSPHY_INTR0_MASK_PLL_LOSS_MASK_Msk 0x2UL
#define USBHSPHY_INTR0_MASK_TEST_PLL_LOCK_MASK_Pos 2UL
#define USBHSPHY_INTR0_MASK_TEST_PLL_LOCK_MASK_Msk 0x4UL
#define USBHSPHY_INTR0_MASK_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Pos 3UL
#define USBHSPHY_INTR0_MASK_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Msk 0x8UL
#define USBHSPHY_INTR0_MASK_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Pos 4UL
#define USBHSPHY_INTR0_MASK_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASK_Msk 0x10UL
#define USBHSPHY_INTR0_MASK_ENABLE_VCCD_MASK_Pos 5UL
#define USBHSPHY_INTR0_MASK_ENABLE_VCCD_MASK_Msk 0x20UL
#define USBHSPHY_INTR0_MASK_ENABLE_HS_VCCD_MASK_Pos 6UL
#define USBHSPHY_INTR0_MASK_ENABLE_HS_VCCD_MASK_Msk 0x40UL
#define USBHSPHY_INTR0_MASK_BISTDONE_MASK_Pos 7UL
#define USBHSPHY_INTR0_MASK_BISTDONE_MASK_Msk 0x80UL
#define USBHSPHY_INTR0_MASK_ERRORFLOW_MASK_Pos 8UL
#define USBHSPHY_INTR0_MASK_ERRORFLOW_MASK_Msk 0x100UL
#define USBHSPHY_INTR0_MASK_STRESS_OUT_MASK_Pos 9UL
#define USBHSPHY_INTR0_MASK_STRESS_OUT_MASK_Msk 0x200UL
#define USBHSPHY_INTR0_MASK_CAL_DONE_MASK_Pos 10UL
#define USBHSPHY_INTR0_MASK_CAL_DONE_MASK_Msk 0x400UL
/* MXS40USBHSDEV_USBHSPHY.INTR0_MASKED */
#define USBHSPHY_INTR0_MASKED_PLL_LOCK_MASKED_Pos 0UL
#define USBHSPHY_INTR0_MASKED_PLL_LOCK_MASKED_Msk 0x1UL
#define USBHSPHY_INTR0_MASKED_PLL_LOSS_MASKED_Pos 1UL
#define USBHSPHY_INTR0_MASKED_PLL_LOSS_MASKED_Msk 0x2UL
#define USBHSPHY_INTR0_MASKED_TEST_PLL_LOCK_MASKED_Pos 2UL
#define USBHSPHY_INTR0_MASKED_TEST_PLL_LOCK_MASKED_Msk 0x4UL
#define USBHSPHY_INTR0_MASKED_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Pos 3UL
#define USBHSPHY_INTR0_MASKED_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Msk 0x8UL
#define USBHSPHY_INTR0_MASKED_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Pos 4UL
#define USBHSPHY_INTR0_MASKED_TEST_PLL_RUN_AWAY_STICKY_CHANGE_MASKED_Msk 0x10UL
#define USBHSPHY_INTR0_MASKED_ENABLE_VCCD_MASKED_Pos 5UL
#define USBHSPHY_INTR0_MASKED_ENABLE_VCCD_MASKED_Msk 0x20UL
#define USBHSPHY_INTR0_MASKED_ENABLE_HS_VCCD_MASKED_Pos 6UL
#define USBHSPHY_INTR0_MASKED_ENABLE_HS_VCCD_MASKED_Msk 0x40UL
#define USBHSPHY_INTR0_MASKED_BISTDONE_MASKED_Pos 7UL
#define USBHSPHY_INTR0_MASKED_BISTDONE_MASKED_Msk 0x80UL
#define USBHSPHY_INTR0_MASKED_ERRORFLOW_MASKED_Pos 8UL
#define USBHSPHY_INTR0_MASKED_ERRORFLOW_MASKED_Msk 0x100UL
#define USBHSPHY_INTR0_MASKED_STRESS_OUT_MASKED_Pos 9UL
#define USBHSPHY_INTR0_MASKED_STRESS_OUT_MASKED_Msk 0x200UL
#define USBHSPHY_INTR0_MASKED_CAL_DONE_MASKED_Pos 10UL
#define USBHSPHY_INTR0_MASKED_CAL_DONE_MASKED_Msk 0x400UL
/* MXS40USBHSDEV_USBHSPHY.SPARE */
#define USBHSPHY_SPARE_DFT_Pos    0UL
#define USBHSPHY_SPARE_DFT_Msk    0xFFFUL
#define USBHSPHY_SPARE_SPARE0_Pos 12UL
#define USBHSPHY_SPARE_SPARE0_Msk 0xFFF000UL
#define USBHSPHY_SPARE_SPARE1_Pos 24UL
#define USBHSPHY_SPARE_SPARE1_Msk 0xFF000000UL
/* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_3 */
#define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPD_Pos 0UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPD_Msk 0x1UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DP_VALUE_Pos 1UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DP_VALUE_Msk 0x2UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DN_VALUE_Pos 2UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPD_DN_VALUE_Msk 0x4UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPU_Pos 3UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_CONN_RPU_Msk 0x8UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPU1_VALUE_Pos 4UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPU1_VALUE_Msk 0x10UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPU2_VALUE_Pos 5UL
#define USBHSPHY_AFE_CONTROL_3_CONN_RPU2_VALUE_Msk 0x20UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_DED_Pos 6UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_DED_Msk 0x40UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_EN_VALUE_Pos 7UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_EN_VALUE_Msk 0x80UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_RESET_VALUE_Pos 8UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_RESET_VALUE_Msk 0x100UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_START_VALUE_Pos 9UL
#define USBHSPHY_AFE_CONTROL_3_HS_DED_START_VALUE_Msk 0x200UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_IREF_EN_Pos 10UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_IREF_EN_Msk 0x400UL
#define USBHSPHY_AFE_CONTROL_3_IREF_EN_VALUE_Pos 11UL
#define USBHSPHY_AFE_CONTROL_3_IREF_EN_VALUE_Msk 0x800UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_EN_Pos 12UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_EN_Msk 0x1000UL
#define USBHSPHY_AFE_CONTROL_3_HS_RX_EN_VALUE_Pos 13UL
#define USBHSPHY_AFE_CONTROL_3_HS_RX_EN_VALUE_Msk 0x2000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_BUF_ON_Pos 14UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_RX_BUF_ON_Msk 0x4000UL
#define USBHSPHY_AFE_CONTROL_3_HS_RX_BUF_ON_VALUE_Pos 15UL
#define USBHSPHY_AFE_CONTROL_3_HS_RX_BUF_ON_VALUE_Msk 0x8000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TED_EN_Pos 16UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TED_EN_Msk 0x10000UL
#define USBHSPHY_AFE_CONTROL_3_HS_TED_EN_VALUE_Pos 17UL
#define USBHSPHY_AFE_CONTROL_3_HS_TED_EN_VALUE_Msk 0x20000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TX_EN_SLOW_Pos 18UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_HS_TX_EN_SLOW_Msk 0x40000UL
#define USBHSPHY_AFE_CONTROL_3_HS_TX_EN_SLOW_VALUE_Pos 19UL
#define USBHSPHY_AFE_CONTROL_3_HS_TX_EN_SLOW_VALUE_Msk 0x80000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_RPU_SEL_Pos 20UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_RPU_SEL_Msk 0x100000UL
#define USBHSPHY_AFE_CONTROL_3_RPU_SEL_VALUE_Pos 21UL
#define USBHSPHY_AFE_CONTROL_3_RPU_SEL_VALUE_Msk 0x200000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DP_Pos 22UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DP_Msk 0x400000UL
#define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DP_VALUE_Pos 23UL
#define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DP_VALUE_Msk 0x800000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DN_Pos 24UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_SE_RX_EN_DN_Msk 0x1000000UL
#define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DN_VALUE_Pos 25UL
#define USBHSPHY_AFE_CONTROL_3_SE_RX_EN_DN_VALUE_Msk 0x2000000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LS_NFS_Pos 26UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LS_NFS_Msk 0x4000000UL
#define USBHSPHY_AFE_CONTROL_3_LS_NFS_VALUE_Pos 27UL
#define USBHSPHY_AFE_CONTROL_3_LS_NFS_VALUE_Msk 0x8000000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LSFS_DIFF_RX_EN_Pos 28UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LSFS_DIFF_RX_EN_Msk 0x10000000UL
#define USBHSPHY_AFE_CONTROL_3_LSFS_DIFF_RX_EN_VALUE_Pos 29UL
#define USBHSPHY_AFE_CONTROL_3_LSFS_DIFF_RX_EN_VALUE_Msk 0x20000000UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LFS_TX_EN_Pos 30UL
#define USBHSPHY_AFE_CONTROL_3_CONTROL_LFS_TX_EN_Msk 0x40000000UL
#define USBHSPHY_AFE_CONTROL_3_LFS_TX_EN_VALUE_Pos 31UL
#define USBHSPHY_AFE_CONTROL_3_LFS_TX_EN_VALUE_Msk 0x80000000UL
/* MXS40USBHSDEV_USBHSPHY.AFE_CONTROL_4 */
#define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_IN_Pos 0UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_IN_Msk 0x1UL
#define USBHSPHY_AFE_CONTROL_4_LFS_TX_IN_VALUE_Pos 1UL
#define USBHSPHY_AFE_CONTROL_4_LFS_TX_IN_VALUE_Msk 0x2UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_ON_Pos 2UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_LFS_TX_ON_Msk 0x4UL
#define USBHSPHY_AFE_CONTROL_4_LFS_TX_ON_VALUE_Pos 3UL
#define USBHSPHY_AFE_CONTROL_4_LFS_TX_ON_VALUE_Msk 0x8UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE0_Pos 4UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE0_Msk 0x10UL
#define USBHSPHY_AFE_CONTROL_4_ENASE0_VALUE_Pos 5UL
#define USBHSPHY_AFE_CONTROL_4_ENASE0_VALUE_Msk 0x20UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE1_Pos 6UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_ENASE1_Msk 0x40UL
#define USBHSPHY_AFE_CONTROL_4_ENASE1_VALUE_Pos 7UL
#define USBHSPHY_AFE_CONTROL_4_ENASE1_VALUE_Msk 0x80UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_CAL_Pos 8UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_CAL_Msk 0x100UL
#define USBHSPHY_AFE_CONTROL_4_CAL_VALUE_Pos 9UL
#define USBHSPHY_AFE_CONTROL_4_CAL_VALUE_Msk 0x3E00UL
#define USBHSPHY_AFE_CONTROL_4_ONCAL_VALUE_Pos 14UL
#define USBHSPHY_AFE_CONTROL_4_ONCAL_VALUE_Msk 0x4000UL
#define USBHSPHY_AFE_CONTROL_4_CAL_F1_VALUE_Pos 15UL
#define USBHSPHY_AFE_CONTROL_4_CAL_F1_VALUE_Msk 0x8000UL
#define USBHSPHY_AFE_CONTROL_4_CAL_F2_VALUE_Pos 16UL
#define USBHSPHY_AFE_CONTROL_4_CAL_F2_VALUE_Msk 0x10000UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_IN_EDN_Pos 17UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_IN_EDN_Msk 0x20000UL
#define USBHSPHY_AFE_CONTROL_4_SE_TX_IN_EDN_VALUE_Pos 18UL
#define USBHSPHY_AFE_CONTROL_4_SE_TX_IN_EDN_VALUE_Msk 0x40000UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_EN_EDN_Pos 19UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_SE_TX_EN_EDN_Msk 0x80000UL
#define USBHSPHY_AFE_CONTROL_4_SE_TX_EN_EDN_VALUE_Pos 20UL
#define USBHSPHY_AFE_CONTROL_4_SE_TX_EN_EDN_VALUE_Msk 0x100000UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_PREE_EN_Pos 21UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_PREE_EN_Msk 0x200000UL
#define USBHSPHY_AFE_CONTROL_4_HS_PREE_EN_VALUE_Pos 22UL
#define USBHSPHY_AFE_CONTROL_4_HS_PREE_EN_VALUE_Msk 0x400000UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TERM_EN_Pos 23UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TERM_EN_Msk 0x800000UL
#define USBHSPHY_AFE_CONTROL_4_HS_TERM_EN_VALUE_Pos 24UL
#define USBHSPHY_AFE_CONTROL_4_HS_TERM_EN_VALUE_Msk 0x1000000UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TX_EN_Pos 25UL
#define USBHSPHY_AFE_CONTROL_4_CONTROL_HS_TX_EN_Msk 0x2000000UL
#define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_VALUE_Pos 26UL
#define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_VALUE_Msk 0x4000000UL
#define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_FAST_VALUE_Pos 27UL
#define USBHSPHY_AFE_CONTROL_4_HS_TX_EN_FAST_VALUE_Msk 0x8000000UL
/* MXS40USBHSDEV_USBHSPHY.UTMI_CONTROL_2 */
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_X6_BIT_Pos 0UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_X6_BIT_Msk 0x7UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_BIT_Pos 3UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_ASSERT_BIT_Msk 0x38UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_X6_BIT_Pos 6UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_X6_BIT_Msk 0x1C0UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_BIT_Pos 9UL
#define USBHSPHY_UTMI_CONTROL_2_DED_RESET_DEASSERT_BIT_Msk 0xE00UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_X6_BIT_Pos 12UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_X6_BIT_Msk 0x7000UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_BIT_Pos 15UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_ASSERT_BIT_Msk 0x38000UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_X6_BIT_Pos 18UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_X6_BIT_Msk 0x1C0000UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_BIT_Pos 21UL
#define USBHSPHY_UTMI_CONTROL_2_DED_START_DEASSERT_BIT_Msk 0xE00000UL
/* MXS40USBHSDEV_USBHSPHY.PLL_TRIMS */
#define USBHSPHY_PLL_TRIMS_RUN_AWAY_Pos 0UL
#define USBHSPHY_PLL_TRIMS_RUN_AWAY_Msk 0x3UL
#define USBHSPHY_PLL_TRIMS_CP_CUR_Pos 2UL
#define USBHSPHY_PLL_TRIMS_CP_CUR_Msk 0xCUL
#define USBHSPHY_PLL_TRIMS_LDO_VCO_Pos 4UL
#define USBHSPHY_PLL_TRIMS_LDO_VCO_Msk 0x70UL
#define USBHSPHY_PLL_TRIMS_LDO_CORE_Pos 7UL
#define USBHSPHY_PLL_TRIMS_LDO_CORE_Msk 0x380UL
#define USBHSPHY_PLL_TRIMS_TEST_RUN_AWAY_Pos 10UL
#define USBHSPHY_PLL_TRIMS_TEST_RUN_AWAY_Msk 0xC00UL
#define USBHSPHY_PLL_TRIMS_TEST_CP_CUR_Pos 12UL
#define USBHSPHY_PLL_TRIMS_TEST_CP_CUR_Msk 0x3000UL
#define USBHSPHY_PLL_TRIMS_TEST_LDO_VCO_Pos 14UL
#define USBHSPHY_PLL_TRIMS_TEST_LDO_VCO_Msk 0x1C000UL
#define USBHSPHY_PLL_TRIMS_TEST_LDO_CORE_Pos 17UL
#define USBHSPHY_PLL_TRIMS_TEST_LDO_CORE_Msk 0xE0000UL
/* MXS40USBHSDEV_USBHSPHY.AFE_TRIMS */
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_Pos 0UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_Msk 0xFUL
#define USBHSPHY_AFE_TRIMS_TRIM_IREF_Pos 4UL
#define USBHSPHY_AFE_TRIMS_TRIM_IREF_Msk 0xF0UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREG_2P5_Pos 8UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREG_2P5_Msk 0xF00UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREG_1P1_Pos 12UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREG_1P1_Msk 0xF000UL
#define USBHSPHY_AFE_TRIMS_TRIM_REG_SW_1P2_Pos 16UL
#define USBHSPHY_AFE_TRIMS_TRIM_REG_SW_1P2_Msk 0xF0000UL
#define USBHSPHY_AFE_TRIMS_TRIM_AFE_HS_IREF_Pos 20UL
#define USBHSPHY_AFE_TRIMS_TRIM_AFE_HS_IREF_Msk 0x700000UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_0_Pos 23UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_0_Msk 0x7800000UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_1_Pos 27UL
#define USBHSPHY_AFE_TRIMS_TRIM_VREF_600M_1_Msk 0x78000000UL


#endif /* _CYIP_MXS40USBHSDEV_H_ */


/* [] END OF FILE */
